A modern processor includes both logic circuitry and memory cell arrays. During operation, the voltage supplied to the processor may be dynamically adapted to its workload requirements. For example, a processor may operate according to Dynamic Voltage Frequency Scaling (DVFS) to achieve significant power savings. However, memory cell arrays are much more sensitive to voltage changes than logic gates. As the transistor threshold voltage variation increases, the memory cell arrays begin to suffer more failures.
A dual power rail architecture separates the memory cell voltage from the logic voltage. This separation allows the memory cells to have a stable voltage within a safe voltage range for nominal static noise margin. The logic voltage may be significantly lowered for dynamic power savings. When dual power rails are implemented, the processor designer has the ability to reduce the power supply significantly in the logic gates while maintaining a safe voltage supply for the memory cell arrays.
To ensure the proper operation of the memory cell array, an operating requirement is that the voltage (Vmem) of the memory cell array should not be lower than the voltage of the logic circuitry (Vlogic). In other words, the operating requirement is: Vmem≧Vlogic. At high voltage operations, Vlogic may experience non-negligible ripples, making it difficult to meet the operating requirement.